IS25LP032D-RGLA3 datasheet(36/118 Pages) ISSI

36 / 118 page

IS25LP032D

IS25WP032D

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A12

08/04/2020

8.2 FAST READ OPERATION (FRD, 0Bh)

The FAST READ (FRD) instruction is used to read memory data at up to a 133MHz clock.

The FAST READ instruction code is followed by three address bytes (A23 - A0) and dummy cycles (configurable,

default is 8 clocks), transmitted via the SI line, with each bit latched-in during the rising edge of SCK. Then the first

data byte from the address is shifted out on the SO line, with each bit shifted out at a maximum frequency fCT,

during the falling edge of SCK.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FAST READ instruction. The FAST READ

instruction is terminated by driving CE# high (VIH).

If the FAST READ instruction is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction

is ignored without affecting the current cycle.

Figure 8.2 Fast Read Sequence

Instruction = 0Bh

3-byte Address

...

CE #

SCK

Data Out

CE #

SCK

High Impedance

...

Mode 3

Mode 0

Dummy Cycles

...

Note: Dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy Cycles.

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