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ATTINY817-MFR. 데이터시트(PDF) 43 Page - Microchip Technology

부품명 ATTINY817-MFR.
상세설명  AVR짰 Microcontroller with Core Independent Peripherals and picoPower짰 Technology
PDF  492 Pages
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제조업체  MICROCHIP [Microchip Technology]
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8.6
Register Summary - CPU
Offset
Name
Bit Pos.
0x04
CCP
7:0
CCP[7:0]
0x05
...
0x0C
Reserved
0x0D
SP
7:0
SP[7:0]
0x0E
15:8
SP[15:8]
0x0F
SREG
7:0
I
T
H
S
V
N
Z
C
8.7
Register Description
8.7.1
Configuration Change Protection
Name: 
CCP
Offset:  0x04
Reset: 
0x00
Property:
 
-
Bit
7
6
5
4
3
2
1
0
CCP[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 7:0 – CCP[7:0]: Configuration Change Protection
Writing the correct signature to this bit field allows changing protected I/O registers or executing protected
instructions within the next four CPU instructions executed.
All interrupts are ignored during these cycles. After these cycles, interrupts will automatically be handled
again by the CPU, and any pending interrupts will be executed according to their level and priority.
When the protected I/O register signature is written, CCP[0] will read as '1' as long as the CCP feature is
enabled.
When the protected self-programming signature is written, CCP[1] will read as '1' as long as the CCP
feature is enabled.
CCP[7:2] will always read as zero.
Value
Name
Description
0x9D
SPM
Allow Self-Programming
0xD8
IOREG
Un-protect protected I/O registers
8.7.2
Stack Pointer
The CPU.SP holds the Stack Pointer (SP) that points to the top of the Stack. After Reset, the Stack
Pointer points to the highest internal SRAM address.
ATtiny417/817
© 2017 Microchip Technology Inc.
Datasheet Complete
DS40001901B-page 43



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