7.3 Feature Description

7.3.1 Smart Config (S-CONF)

This S-CONF pin configures the device based on the resistor value. This pin is read after EN/SYNC goes high.

The device configuration cannot be changed during operation. The S-CONF value is re-read if EN is pulled

below 200 mV or if VIN falls below UVLO. Table 7-1 shows the configuration options of switching frequency,

spread spectrum modulation, output discharge, and synchronization.

Table 7-1. S-CONF Device Configuration Modes

S-CONF

SWITCHING

FREQUENCY

SPREAD SPECTRUM

OUTPUT

DISCHARGE

SYNCHRONIZATION

VIN

2.2 MHz

OFF

OFF

No

GND

1 MHz

OFF

OFF

No

4.87 kΩ

2.2 MHz

OFF

OFF

1.9 MHz to 2.42 MHz

7.5 kΩ

2.2 MHz

Random

OFF

No

9.31 kΩ

1 MHz

OFF

OFF

0.9 MHz to 1.2 MHz

14.3 kΩ

1 MHz

Random

OFF

No

Discharge On

18.2 kΩ

2.2 MHz

OFF

ON

No

22.1 kΩ

1 MHz

OFF

ON

No

27.4 kΩ

2.2 MHz

OFF

ON

1.9 MHz to 2.42 MHz

42.2 kΩ

2.2 MHz

Random

ON

No

52.3 kΩ

1 MHz

OFF

ON

0.9 MHz to 1.2 MHz

80.6 kΩ

1 MHz

Random

ON

No

7.3.2 Device Enable (EN/SYNC)

The device is enabled by pulling the EN/SYNC pin high, and has an accurate rising threshold voltage of typically

1.01 V. Once the device is enabled, the operation mode is set by the configuration of the S-CONF pin. This

depending on the selected S-CONF value. It is shortest with smaller S-CONF resistors.

case the EN/SYNC pin cannot be driven to a low level. The pulldown resistor is disconnected after start-up. With

EN set to a low level, the device enters shutdown and the pulldown resistor is activated again.

7.3.3 Device Synchronization (EN/SYNC)

The EN/SYNC pin is also used for device synchronization. Once a clock signal is applied to this pin, the device is

enabled and reads the configuration of the S-CONF pin. The external clock frequency must be within the clock

synchronization frequency range set by the S-CONF pin. When the clock signal changes from a clock to a static

high, then the device switches from external clock to internal clock. To shutdown the device when using an

external clock, EN/SYNC must go low for at least 10 µs.

The clock signal can be a logic signal with a logic level as specified in the electrical table, and can be applied

directly to the EN/SYNC pin. External logic, such as an AND gate, can be used to combine separate enable and

clock inputs, as shown in Figure 7-1.

TPS6291x

EN/SYNC

EN/SYNC

EN

CLK

Figure 7-1. Synchronization with Separate Enable Signal (optional)

TPS62912, TPS62913

SLVSFP4 – AUGUST 2020

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