7.3.4 Spread Spectrum Modulation

Using the S-CONF pin enables or disables spread spectrum modulation. DC/DC converters generate an output

voltage ripple at the switching frequency. When powering ADCs or an analog front-end (AFE), the switching

frequency generates high frequency mixing spurs as well as a low frequency spur in the output frequency

spectrum. Using the optional second stage L-C filter reduces the ripple of the converter and spurs by up to 30

dB. Using a random spread spectrum modulation also reduces the spurs in the output spectrum as shown in

Figure 6-2.

Spread spectrum uses a random modulation to spread the switching frequency over a larger frequency range.

The randomized modulation generates several lower amplitude spurs at frequencies below 10 kHz, and avoids a

single low frequency tone generated by the modulation frequency. The frequency spread is 20% of the switching

frequency with a modulation frequency of 180 Hz. The frequency spreading is shown in Figure 7-2.

f

V

Figure 7-2. Randomized Spread Spectrum Modulation

7.3.5 Output Discharge

Output discharge is enabled or disabled, depending on the S-CONF setting. With output discharge enabled, the

enabled during thermal shutdown, UVLO, or when EN/SYNC is pulled low.

7.3.6 Undervoltage Lockout (UVLO)

To avoid mis-operation of the device at low input voltages, the device is enabled once the input voltage is above

the undervoltage lockout threshold. The device is disabled once the input voltage falls below the undervoltage

threshold.

7.3.7 Power-Good Output

The device has a power-good output. The PG pin goes high impedance once the FB pin voltage is above 95% of

the nominal voltage, and is driven low once the voltage falls below typically 90% of the nominal voltage. Table

7-2 shows the typical PG pin logic. The PG pin is an open-drain output and is specified to sink up to 10 mA. The

power-good output requires a pullup resistor connecting to any voltage rail less than 18 V. The PG signal can be

used for sequencing of multiple rails by connecting to the EN pin of other converters. If not used, the PG pin can

be left floating or connected to GND. PG has a deglitch time of typically 8 μs before going low.

Table 7-2. Power Good Pin Logic

DEVICE STATE

PG LOGIC STATUS

HIGH IMPEDANCE

LOW

Enabled (EN/SYNC = High)

√

√

Shutdown (EN/SYNC = Low)

√

UVLO

√

Thermal Shutdown

√

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TPS62912, TPS62913

SLVSFP4 – AUGUST 2020

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