ADP1032ACPZ-3-R7 datasheet(6/37 Pages) AD

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ADP1032

Data Sheet

Rev. 0 | Page 6 of 37

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

Channel Matching

Codirectional

tPSKCD

0.5

5.5

Opposing Direction

tPSKOD

0.5

Propagation Delay

tPHL, tPLH

50% input to 50% output

VMVDD = 5 V, VSVDD1 = 5 V

VMVDD = 3.3 V, VSVDD1 = 5 V

VMVDD = 3.3 V, VSVDD1 = 3.3 V

8.5

VMVDD = 2.3 V, VSVDD1 = 1.8 V

Jitter

620

ps p-p

VMVDD = 5 V, VSVDD1 = 5 V

100

ps rms

VMVDD = 5 V, VSVDD1 = 5 V

440

ps p-p

VMVDD = 3.3 V, VSVDD1 = 5 V

ps rms

VMVDD = 3.3 V, VSVDD1 = 5 V

290

ps p-p

VMVDD = 3.3 V, VSVDD1 = 3.3 V

ps rms

VMVDD = 3.3 V, VSVDD1 = 3.3 V

410

ps p-p

VMVDD = 2.3 V, VSVDD1 = 1.8 V

110

ps rms

VMVDD = 2.3 V, VSVDD1 = 1.8 V

MGPI1, MGPI2, SGPI3

Data Rate

100

kbps

Input Pulse Width

tPW

μs

Within PWD limit

Propagation Delay

tPHL, tPLH

μs

50% input to 50% output

Jitter

19.5

μs

ISOLATORS AC SPECIFICATIONS

General-Purpose Input/Output

(GPIO)

Output Rise Time/Fall Time

tR/tF

2.5

10% to 90%

SPI

Output Rise Time/Fall Time

tR/tF

10% to 90%

Common-Mode Transient

Immunity7

|CM|

100

kV/μs

1 VIx is the Channel x logic input, where Channel x can be MCK, MO, SO, MGPI1, MGPI2, or SGPI3.

2 VxVDD = VMVDD or VSVDDx. In these places, either VMVDD or VSVDDx can be used.

3 IOx is the output current of the pin.

4 VIXH is the input side, logic high.

5 VIXL is the input side, logic low.

6 VOX is the voltage where the output is pulled.

7 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 MVDD and/or SVDDx. The common-mode voltage slew

rates apply to both rising and falling common-mode voltage edges.

ADP1032ACPZ-3-R7 데이터시트(PDF) 6 Page - Analog Devices

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