VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

-ii-

Table of Contents

Technologies, Inc.

We Connect

We Connect

We Connect

We Connect

REVISION HISTORY ....................................................................................................................................................................... I

TABLE OF CONTENTS ..................................................................................................................................................................II

LIST OF FIGURES......................................................................................................................................................................... IV

LIST OF TABLES........................................................................................................................................................................... IV

OVERVIEW .......................................................................................................................................................................................3

PINOUTS ............................................................................................................................................................................................5

PIN DIAGRAM.................................................................................................................................................................................5

PIN LIST..........................................................................................................................................................................................8

PIN DESCRIPTIONS.......................................................................................................................................................................10

REGISTERS .....................................................................................................................................................................................15

REGISTER OVERVIEW..................................................................................................................................................................15

PCI Function 0 Registers – Link Controller.......................................................................................................................15

Memory-Space Registers – Link Controller .......................................................................................................................16

PHY Registers .......................................................................................................................................................................18

REGISTER DESCRIPTIONS............................................................................................................................................................19

Link Controller Configuration Registers (PCI Function 0) ..............................................................................................19

Configuration Space Header ..................................................................................................................................................................19

Controller-Specific Configuration Registers..........................................................................................................................................20

Power Management Registers................................................................................................................................................................21

Link Controller Memory-Space Registers ..........................................................................................................................22

Autonomous CSR Resources .................................................................................................................................................................23

Bus Management CSR Registers ...........................................................................................................................................................23

HC Control Registers.............................................................................................................................................................................25

Self-ID Control Registers ......................................................................................................................................................................26

Channel Mask Registers ........................................................................................................................................................................26

Interrupt Registers..................................................................................................................................................................................27

Link Control Registers...........................................................................................................................................................................29

PHY Control Registers ..........................................................................................................................................................................30

Cycle Timer Registers............................................................................................................................................................................30

Filter Registers.......................................................................................................................................................................................31

Asynchronous Transmit & Receive Context Registers ..........................................................................................................................32

Isochronous Transmit Context Registers ...............................................................................................................................................34

Isochronous Receive Context Registers.................................................................................................................................................35

PHY Registers .......................................................................................................................................................................37

PHY Register Overview.........................................................................................................................................................................37

PHY Register Bit Field Descriptions .....................................................................................................................................................37

PHY Register Page 0 - Port Status.........................................................................................................................................................38

PHY Register Page 1 - Vendor Identification........................................................................................................................................38

PHY Register Page 7 - Vendor-Dependent............................................................................................................................................39

FUNCTIONAL DESCRIPTIONS...................................................................................................................................................40

PHY GENERAL DESCRIPTION.....................................................................................................................................................40

Cable Interface ......................................................................................................................................................................40

PHY CIRCUIT DESCRIPTION.......................................................................................................................................................41

Pinless PLL and Clock Generation......................................................................................................................................41

Power Down and Auto Power Save .....................................................................................................................................41

Data Transmission ................................................................................................................................................................41