VT6307 datasheet(42/54 Pages) VIA

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VT6307 PCI 1394a Host Controller

Revision 1.2 October 1, 2002

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Active

.............................................. default = 0

This bit is set by the chip when software sets the run

bit or sets the wake bit while the run bit is set. The

chip will clear this bit:

When a branch is indicated by a descriptor but

the Z value of the branch address is 0

When software clears the run bit and the chip

has reached a safe stopping point

While the dead bit is set

After a hardware or software reset

When this bit is cleared and the run bit is clear, the

chip will set the Interrupt Event bit for the context.

9-7

Reserved

........................................ always reads 0

6-5

Speed

This field indicates the speed at which the packet was

received or transmitted:

00 100 Mbits/sec

01 200 Mbits/sec

10 400 Mbits/sec

11 -reserved-

4-0

Ack / Err Code.......................................... default = 0

Following an “Input” command, this field contains

the error code.

For “Buffer Fill” mode, possible values are: “Ack

Complete”, “Ack Data Error”, “Event Overrun”,

“Event Descriptor Read”, “Event Data Write”, and

“Event Unknown” (see “Table 6.

Packet Event

Codes” for descriptions and values for these codes).

For “Packet-Per-Buffer” mode, possible values are:

“Ack Complete”, “Ack Data Error”, “Event Short

Packet”, “Event Long Packet”, “Event Overrun”,

“Event Descriptor Read”, “Event Data Write”, and

“Event Unknown” (see “Table 6.

Packet Event

Codes” for descriptions and values for these codes).

Offset 40C – Isoch Receive Context 0 Command Ptr .... RW

Offset 42C – Isoch Receive Context 1 Command Ptr .... RW

Offset 44C – Isoch Receive Context 2 Command Ptr .... RW

Offset 46C – Isoch Receive Context 3 Command Ptr .... RW

Offset 410 – Isoch Receive Context 0 Match .................. RW

Offset 430 – Isoch Receive Context 1 Match .................. RW

Offset 450 – Isoch Receive Context 2 Match .................. RW

Offset 470 – Isoch Receive Context 3 Match .................. RW

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