28

Am29N323D

August 8, 2002

AC CHARACTERISTICS

Synchronous/Burst Read

Notes:

1. Figure shows total number of wait states set to five cycles. The total number of wait states can be programmed from four

cycles to seven cycles.

2. Figure shows that PS (power saving mode) has been enabled; one additional wait state occurs during initial data Da. Latency

is not present if PS is not enabled.

3. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.

Figure 9.

Burst Mode Read

Parameter

Description

11A

(40 MHz)

Unit

JEDEC

Standard

Initial Access Time

Max

120

ns

Burst Access Time Valid Clock to Output Delay

Max

20

ns

AVD# Setup Time to CLK

Min

5

ns

AVD# Hold Time from CLK

Min

7

ns

AVD# High to OE# Low

Min

0

ns

Address Setup Time to CLK

Min

5

ns

Address Hold Time from CLK

Min

7

ns

Data Hold Time from Next Clock Cycle

Max

4

ns

Output Enable to Data, PS, or RDY Valid

Max

20

ns

Chip Enable to High Z

Max

10

ns

Output Enable to High Z

Max

10

ns

CE# Setup Time to CLK

Min

5

ns

RDY Setup Time to CLK

Min

5

ns

Ready access time from CLK

Max

20

ns

Da

Da + 1

Da + 2

Da + n

OE#

A/DQ0:

A/DQ15

A16:

A20

Aa

AVD#

RDY

CLK

CE#

Aa

5 cycles for initial access shown.

Programmable wait state function is set to 01h.

1 cycle

wait state

when PS

enabled

25 ns typ.

Hi-Z

Hi-Z

Hi-Z