AGLP030 datasheet(89/128 Pages) ACTEL

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IGLOO PLUS Low Power Flash FPGAs

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Timing Characteristics

1.5 V DC Core Voltage

Table 2-96 • FIFO

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter

Description

Std.

Units

tENS

REN_B, WEN_B Setup Time

1.66

tENH

REN_B, WEN_B Hold Time

0.13

tBKS

BLK_B Setup Time

0.30

tBKH

BLK_B Hold Time

0.00

tDS

Input Data (DI) Setup Time

0.63

tDH

Input Data (DI) Hold Time

0.20

tCKQ1

Clock High to New Data Valid on DO (flow-through)

2.77

tCKQ2

Clock High to New Data Valid on DO (pipelined)

1.50

tRCKEF

RCLK High to Empty Flag Valid

2.94

tWCKFF

WCLK High to Full Flag Valid

2.79

tCKAF

Clock High to Almost Empty/Full Flag Valid

10.71

tRSTFG

RESET_B Low to Empty/Full Flag Valid

2.90

tRSTAF

RESET_B Low to Almost Empty/Full Flag Valid

10.60

tRSTBQ

RESET_B Low to Data Out Low on DO (flow-through)

1.68

RESET_B Low to Data Out Low on DO (pipelined)

1.68

tREMRSTB

RESET_B Removal

0.51

tRECRSTB

RESET_B Recovery

2.68

tMPWRSTB

RESET_B Minimum Pulse Width

0.68

tCYC

Clock Cycle Time

6.24

FMAX

Maximum Frequency for FIFO

160

MHz

Note:

For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

AGLP030 데이터시트(PDF) 89 Page - Actel Corporation

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