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AGLP030 데이터시트(PDF) 55 Page - Actel Corporation |
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AGLP030 데이터시트(HTML) 55 Page - Actel Corporation |
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55 / 128 page ![]() IGLOO PLUS Low Power Flash FPGAs Re vi s i on 11 2 - 41 I/O Register Specifications Fully Registered I/O Buffers with Asynchronous Preset Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset INBUF CLKBUF Data Input I/O Register with: Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Preset Postive-Edge Triggered CLK Preset Data_out Data EOUT DOUT DQ DFN1P1 PRE DQ DFN1P1 PRE DQ DFN1P1 PRE A C D E F H I J L Y Core Array |
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