4

Features

4.1

Chip enable register

As the M24128X is delivered in 4-ball WLCSP without chip enable inputs, the device provides a non-volatile 8-bit

register allowing the user to define a configurable device address (CDA) and a software write protection. This

register can be written and read with the device type identifier (1010b) and with a specific address.The description

of the chip enable register is given Table 3.

bit 7 bit 6 bit 5 bit 4

bit 3

bit 2

bit 1

bit 0

x (1)

x(1)

x(1)

x(1)

C2

C1

C0

b0

Configurable device

address bit

Configurable device

address bit

Configurable device

address bit

SWP: Write protection

activation bit

1. x = Don’t care bits. Factory delivery of the register is X0b

Bit 7:4

Don’t care bits

Bits 3:1

Chip enable address configuration:

•

(b3,b2,b1) = (0,0,0): the chip enable address is 000 (factory delivery value)

•

(b3,b2,b1) = (0,0,1): the chip enable address is 001

•

(b3,b2,b1) = (0,1,0): the chip enable address is 010

•

(b3,b2,b1) = (1,0,0): the chip enable address is 100

•

(b3,b2,b1) = (1,1,0): the chip enable address is 110

•

(b3,b2,b1) = (1,1,1): the chip enable address is 111

•

(b3,b2,b1) = (0,1,1): the chip enable address is 011

•

(b3,b2,b1) = (1,0,1): the chip enable address is 101

Bit 0

Enables or disables the write protection of the memory array:

•

b0 = 0: the whole memory array can be written and read (factory delivery value)

•

b0 = 1: the whole memory array is write protected and is in read-only mode

4.2

Configurable device address

C2, C1 and C0 are defining the chip enable address in the Device Select Code. These bits can be written and re-

configured with a Write command.

Factory delivery value is 000b.

At power up or after reprogramming, the device will load the last configuration of C2, C1 and C0 values.

4.3

Software write protect

In order to prevent unwanted write sequence, the M24128X offers the SWP feature, which makes it possible to

protect the whole memory content. write operations are disabled (read-only memory) when the SWP is set to 1

(SWP=1b). In the same way, the write operations are enabled when the SWP is set to 0 (SWP=0b).

Factory default values is 0b.

At power up, the device will load the last configuration of the SWP value.

Updating the SWP to a new value is a reversible action: the SWP bit can be updated from 0 to 1 and from 1 to 0.

When SWP is set to '1', device select and address bytes are acknowledged, data bytes are not acknowledged.

M24128X-FCU

Features

DS12680 - Rev 2

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