ZSC31014 datasheet(23/59 Pages) RENESAS

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ZSC31014 Datasheet

January 20, 2016

Figure 2.5

SPI Bus Data Output Timing

(See section 3.1 for data transmission details.)

2.3.6. Clock Generator / Power-On Reset (CLKPOR)

The ZSC31014 has an internal 4MHz temperature-compensated oscillator that provides the time base for all

operations. This oscillator feeds into a 4:1 post scalar that can optionally form the clock source for the device.

Using ClkSpeed (bit 3 of EEPROM word 01HEX; see section 3.6) the user can select a 4MHz clock or a 1MHz

digital core clock for the ZSC31014. If the fast response times and sampling periods provided by the 4MHz clock

are not needed, then choosing the 1MHz clock will result in better noise performance.

If the power supply exceeds the power-on reset level (see Table 1.3), the reset signal de-asserts and the clock

generator starts working at the selected frequency (approximately 1MHz or 4MHz). The exact value only

influences the conversion cycle time. To minimize the oscillator error as the VDD voltage changes, an on-chip

regulator supplies the oscillator block.

2.4. Diagnostic Features

The ZSC31014 offers a full suite of diagnostic features to ensure robust system operation in the most “mission-

critical” applications. The diagnostic states are indicated by a transmission of the status of the 2 MSBs of the

bridge high byte data.

tBUS

tLOW

SCLK

MISO

HiZ

tHDSS

tHIGH

tCLKD

tSUSS

HiZ

tCLKD

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