TSC2012IDT datasheet(36/54 Pages) STMICROELECTRONICS

36 / 54 page

If a single channel is used, for sure the change on the sample and hold capacitance are very small, and so the

recovery time is extremely low as described by the figure below.

Figure 66. Capacitive load response at Vcc = 3.3 V with a step of 100 mV

-4µ

4µ

8µ

12µ

-100

-80

-60

-40

-20

100

-1000

-900

-800

-700

-600

-500

-400

-300

-200

-100

100

200

300

400

500

600

700

800

900

1000

Time (s)

Sample and hold

Vout

Vcc=3.3V, Vicm=1.65V, Vsense=0Vpp

T=25°C,

50kHz square signal of 100mV amplitude

injected in the output through 40pF

The effect of the ADC sampling and hold can be easily smoothed thanks to an RC filter. As suggested on the

schematic below. The capacitor of the external filter must be chosen much higher than the internal ADC capacitor,

in order to easily absorb the sudden voltage variation on the output due to the sampling and hold of the ADC. The

resistance must be chosen accordingly to the application speed of the system in order not to impact the whole

application. The main advantage of using an RC filter is to have an antialiasing system. For sure the used ADC

must have sample and hold conversion in accordance with the RC filter value, in order to let the output recover

before sampling.

Figure 67. RC filter when driving ADC

In the figure Figure 68. Capacitive load response at Vcc = 3.3 V with 720 kHz RC filter an Rs = 470 Ω resistance

and a Ct = 470 pF capacitance have been set. Given a low-pass filter of 720 kHz and a response time of roughly

660 ns.

In the figure Figure 69. Capacitive load response at Vcc = 3.3 V with 194 kHz RC filter an Rs = 820 Ω resistance

and a Ct = 1 nF capacitance have been set. Given a low-pass filter of 194 kHz and a response time of roughly 2.5

µs.

TSC2010, TSC2011, TSC2012

Stability

DS13057 - Rev 4

page 36/54

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