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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADA4355ABCZ 데이터시트(PDF) 44 Page - Analog Devices |
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ADA4355ABCZ 데이터시트(HTML) 44 Page - Analog Devices |
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44 / 45 page  ADA4355 Data Sheet Rev. A | Page 44 of 45 Serial Output Data Control (Register 0x21) The power-on default value of this register is 0x30. The serial output data control register programs the ADA4355 in various output data modes, depending on the data capture solution. Table 21 describes the various serialization options available in the ADA4355. Note that, in single data rate (SDR) mode, the DCO frequency is double that of the frequency in DDR mode for a given sample rate. In SDR mode, to stay within the capability of the DCO LVDS driver, reduce the ADC sample rate to ≤62.5 MSPS to keep the DCO frequency at ≤500 MHz. User Input/Output Control 2 (Register 0x101) The power-on default value of this register is 0x00. Bits[7:1]—Open Bit 0—Disable SDIO Pull-Down Bit 0 can be set to disable the internal 31 kΩ pull-down resistor on the SDIO ball, which limits the loading when many devices are connected to the SPI bus. Table 21. Register 0x21 Options Serialization Options Selected Register 0x21 Contents Serial Output Number of Bits (SONB) Frame Mode Serial Data Mode DCO Multiplier Timing Diagram 0x30 16-bit 1× DDR two-lane bytewise 4 × fS See Figure 6 (default setting) 0x20 16-bit 1× DDR two-lane bitwise 4 × fS See Figure 6 0x10 16-bit 1× SDR two-lane bytewise 8 × fS See Figure 6 0x00 16-bit 1× SDR two-lane bitwise 8 × fS See Figure 6 0x34 16-bit 2× DDR two-lane bytewise 4 × fS See Figure 8 0x24 16-bit 2× DDR two-lane bitwise 4 × fS See Figure 8 0x14 16-bit 2× SDR two-lane bytewise 8 × fS See Figure 8 0x04 16-bit 2× SDR two-lane bitwise 8 × fS See Figure 8 0x40 16-bit 1× DDR one-lane wordwise 8 × fS See Figure 10 0x32 12-bit 1× DDR two-lane bytewise 3 × fS See Figure 7 0x22 12-bit 1× DDR two-lane bitwise 3 × fS See Figure 7 0x12 12-bit 1× SDR two-lane bytewise 6 × fS See Figure 7 0x02 12-bit 1× SDR two-lane bitwise 6 × fS See Figure 7 0x36 12-bit 2× DDR two-lane bytewise 3 × fS See Figure 9 0x26 12-bit 2× DDR two-lane bitwise 3 × fS See Figure 9 0x16 12-bit 2× SDR two-lane bytewise 6 × fS See Figure 9 0x06 12-bit 2× SDR two-lane bitwise 6 × fS See Figure 9 0x42 12-bit 1× DDR one-lane wordwise 6 × fS See Figure 11 |
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