GC5316 datasheet(72/75 Pages) TI

72 / 75 page

GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

www.ti.com

7.6

AC Characteristics

PARAMETER

MIN

MAX

UNIT

FCK

Clock frequency (adcclk, rxclk, txclk) in selected modes(6)(9)

125

MHz

FCK

Clock frequency (adcclk, rxclk, txclk) unrestricted(6)

MHz

tADCKL

tRXCKL

tTXCKL

Clock low period (below VIL) (adcclk, rxclk, txclk)(6)

tADCKH

tRXCKH

tTXCKH

Clock high period (above VIH) (adcclk, rxclk, txclk)(6)

tr, tf

Clock rise and fall times (VIL to VIH) (adcclk, rxclk, txclk)(8)

tsu(TX)

Input setup (txin_[0−11]_[a−b], tx_sync[a−d]) before txclk rises(6)

2.2

tsu(RX)

Input setup (rx_sync[a−d]) before rxclk rises(6)

2.5

tsu(RXB)

Input setup (rxin_[a−d]_[0−15]) before rxclk rises adc_fifo bypassed(6)

0.4

tsu(AD)

Input setup (rxin[a−d]_[0−15]) before adcclk rises adc_fifo active(6)

2.2

th(TX)

Input hold (txin_[0−11]_[a−b], tx_sync[a−d]) after txclk rises(6)

1.1

th(RX)

Input hold (rx_sync[a−d]) after rxclk rises(6)

0.5

th(RXB)

Input hold (rxin[a−d]_[0−15]) after rxclk rises adc_fifo bypassed(6)

3.5

th(AD)

Input hold (rxin[a−d]_[0−15]) after adcclk rises adc_fifo active(6)

td(TX)

Data output delay (tx_sync_out_[0−5], tx_iflag, txout_[a−d]_[0−17]) after txclk rises(6)

6.5

td(RX)

Data output delay (rx_sync_out_[0−5], rxout_[0−11] _[a−d]) after rxclk rises(6)

6.5

tOH(TX)

Data output hold (tx_sync_out_[0−5], tx_iflag, txout_[a−d]_[0−17]) after txclk rises(6)

1.5

tOH(RX)

Data output hold (rx_sync_out_[0−5], rxout_[0−11] _[a−d]) after rxclk rises(6)

1.5

FJCK

JTAG clock frequency (tck)(6)

MHz

tJCKL

JTAG clock low period (below VIL) (tck)(6)

tJCKH

JTAG clock high period (above VIH) (tck)(6)

tsu(J)

JTAG input (tdi or tms) setup before tck goes high(6)

th(J)

JTAG input (tdi or tms) hold time after tck goes high(6)

td(J)

JTAG output (tdo) delay from falling edge of tck(6)

tsu(UPA)

Microprocessor address setup to falling edge of controls(6)

2.5

th(UPA)

Microprocessor address hold from rising edge of controls(6)

tsu(UPD)

Microprocessor data setup to rising edge of controls during writes(6)

th(UPD)

Microprocessor data hold from rising edge of controls during writes(6)

2.6

Microprocessor data output hold from rising edge of controls (read)(7)

td(UP)

Microprocessor data output delay from falling edge of controls (read)(6)

tUPCKL

Microprocessor control low time(6)

tUPCKH

Microprocessor control high time(6)

8.4

NOTE: Timing is measured from the respective clock at V

PAD /2 to input or output at VPAD /2. Output loading is a 50-Ω transmission line whose delay is

calibrated out.

(6) Each part is tested at 90°C case temperature for the given specification. Lots are sample tested at −40°C.

(7) Controlled by design and process and not directly tested. Verified on initial part evaluation.

(8) Recommended practice.

(9) Excluding rx_sync_out , rx_sync_out_[1−5], tx_sync_out, tx_sync_out_[1−5]. Resampler active or adcclk < 80 MHz.

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