GC5316 datasheet(24/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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Figure 19 shows the DDC serial output timing.

tsu

tpd

rx_sync can be a pulse or level − interface will generat periodic frame strobes using programmed sync interval

1 rxclk + programmable bit time

rxclk

rx_sync

rx_sync_out

rxout

(serial output data)

2 txclk

(programmable)

Note: With half-rate serial output, the MSB comes out 5 rxclks after rx_sync.

With full-rate serial output, the MSB comes out 4 rxclks after rx_sync.

MSB

(pser_recv_fsdel=0

pser_recv__clkdiv = 1)

Figure 19. DDC Serial Output Timing

Table 20. Programming

VARIABLE

DESCRIPTION

pser_recv_fsinvl(6:0)

Frame sync interval in bits

pser_recv_bits(4:0)

Number of data output bits − 1. i.e.: 10001 = 18 bits

pser_recv_clkdiv(3:0)

Receive serial interface clock divider rate − 1.

0= rxclk, 15= rxclk/16

pser_recv_8pin

When set, configures the serial out pins for 4I and 4Q in UMTS mode. When clear, the mode is 2I and

2Q. Used in conjunction with pser_recv_alt.

pser_recv_alt

When set, outputs Q data from adjacent DDC channel.

pser_recv_fsdel(1:0)

Number of bit clocks the frame sync is output early with respect to serial data.

ssel_serial(2:0)

Sync source (1 of 8).

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