FXLS8964AF datasheet(62/98 Pages) NXP

62 / 98 page

NXP Semiconductors

FXLS8964AF

3-Axis Low-g Accelerometer

FXLS8964AF

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Objective data sheet

Rev. 2 — 30 October 2020

62 / 98

Table 70. INT_EN register (address 20h) bit allocation

Bit

Name

DRDY_

BUF_EN

SDCD_

OT_EN

SDCD_

WT_EN

ORIENT_

ASLP_EN BOOT_

DIS

WAKE_

OUT_EN

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 71. INT_EN register (address 20h) bit description

Field

Description

DRDY_EN

Data-ready interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as configured by the

setting made in INT_PIN_SEL.

Note: When BT_MODE = GND, SRC_DRDY bit and the signalled interrupt is cleared whenever one

or more of the VECM, and OUT_X/Y/Z registers are read. When BT_MODE = VDD, SRC_DRDY bit

is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are read. However the

data ready interrupt is signalled for TPULSE-MOT s (5 ms typ) and it clears itself automatically. The

current data ready interrupt pulse will be terminated when the device is transitioned into STANDBY

mode before its completion and thus may not span for entire TPULSE-MOT s.

BUF_EN

Output data buffer interrupt output enable

0 Interrupt is not routed to the INTx output pins (default)

1: Interrupt is routed to either the INT1 or INT2 output pins as configured by the setting made in

INT_

PIN_SEL.

SDCD_OT_EN

SDCD outside of thresholds interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is routed to either the INT1 or INT2 output pin as configured by the setting made in INT_

PIN_SEL.

SDCD_WT_EN

SDCD within thresholds interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is routed to either the INT1 or INT2 output pins as configured by the setting made in INT_

PIN_SEL.

ORIENT_EN

Orientation interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as determined by the

setting made in INT_PIN_SEL.

ASLP_EN

Auto-WAKE/SLEEP interrupt output enable

0 (default): Interrupt is disabled.

1: Interrupt is enabled and signaled on either the INT1 or INT2 output pins as determined by the

setting made in INT_PIN_SEL.

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