PRT2011CVL4A datasheet(4/113 Pages) NXP

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i.MX RT1064 Crossover Processors for Industrial Products, Rev. 2, 08/2020

NXP Semiconductors

i.MX RT1064 Introduction

— Two Ultra Secure Digital Host Controller (uSDHC) interfaces

– MMC 4.5 compliance with HS200 support up to 200 MB/sec

– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec

– Support for SDXC (extended capacity)

— Two 10/100M Ethernet controller with support for IEEE1588

— Eight universal asynchronous receiver/transmitter (UARTs) modules

— Four I2C modules

— Four SPI modules

— Two FlexCAN modules

— FlexCAN (with Flexible Data-Rate supported)

— Three FlexIO modules

•

GPIO and Pin Multiplexing:

— General-purpose input/output (GPIO) modules with interrupt capability

— Input/output multiplexing controller (IOMUXC) to provide centralized pad control

The i.MX RT1064 processors integrate advanced power management unit and controllers:

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Full PMIC integration, including on-chip DCDC and LDO

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Temperature sensor with programmable trim points

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GPC hardware power management controller

The i.MX RT1064 processors support the following system debug:

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Arm CoreSight debug and trace architecture

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Trace Port Interface Unit (TPIU) to support off-chip real-time trace

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Cross Triggering Interface (CTI)

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Support for 5-pin (JTAG) and SWD debug interfaces

The i.MX RT1064 processors support the following analog interfaces:

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Two Analog-Digital-Converters (ADC), 16-channel for each, 20-channel in total, 1MSPS

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Two Digital-Analog-Converters (DAC)

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Four Analog Comparators (ACMP)

Security functions are enabled and accelerated by the following hardware:

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High Assurance Boot (HAB)

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Data Co-Processor (DCP):

— AES-128, ECB, and CBC mode

— SHA-1 and SHA-256

— CRC-32

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Bus Encryption Engine (BEE)

— AES-128, ECB, and CTR mode

— On-the-fly QSPI Flash decryption

•

True random number generation (TRNG)

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