Shenzhen H&M Semiconductor Co.Ltd

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Figure 2. Start and Stop Definition

Figure 3. Output Acknowledge

3. Device Addressing

The 128K/256K/512K EEPROM devices all require an 8-bit device address word following a start

condition to enable the chip for a read or write operation (see to Figure 4 on page 5).

The device address word consists of a mandatory “1”, “0” sequence for the first four most

significant bits as shown. This is common to all the Serial EEPROM devices.

The 128K/256K /512K uses the three device address bits A2, A1, A0 to allow as many

as eight devices on the same bus. These bits must compare to their corresponding