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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LTM4651 데이터시트(PDF) 5 Page - Analog Devices |
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LTM4651 데이터시트(HTML) 5 Page - Analog Devices |
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5 / 54 page  LTM4655 5 Rev. 0 For more information www.analog.com ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified internal operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 1 (positive-VOUTn+, noninverting step-down configuration with VOUTn– = GND), VINn = SVINn = 36V, EXTVCCn = 24V, RUNn = 3.3V, RISETn = 480k, RfSETn+ = 57.6kΩ, fSWn = 1.5MHz (CLKINn driven with 1.5MHz clock signal) and voltages referred to GND unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSn VOUTn+ Ripple Frequency RfSETn = 57.6k, CLKINn Open Circuit l 1.7 1.95 2.2 MHz ∆VOUTn(START)+ Turn-On Overshoot 8 mV tSTARTn Turn-On Start-Up Time Delay Measured from VINn Toggling from 0V to 36V to PGOOD n Exceeding 3V; PGOODn. Having a 100kΩ Pull-Up to 3.3V with Respect to GND, VPGFB n Resistor Divider Network as Shown in Test Circuit 1, RISETna = 480kΩ and ISET na Electrically Connected to ISETnb and CLKIN Driven with 1.5MHz Clock l 4 9 ms ∆VOUTn(LS)+ Peak Output Voltage Deviation for Dynamic Load Step IOUTn+: 0A to 2A and 2A to 0A Load Steps in 1μs, COUTHn = 47µF × 2 400 mV tSETTLEn Settling Time for Dynamic Load Step IOUTn+: 0A to 2A and 2A to 0A Load Steps in 1μs, COUTHn = 47µF × 2 50 µs IOUTn(OCL)+ IOUTn+ Output Current Limit 5.5 A Control Section IISETna Reference Current of ISET na Pin VISETna = 0.5V, 3.1V ≤ VINn ≤ 13.2V VISETna = 24V, 29V ≤ VINn ≤ 40V l l 49.3 49 50 50 50.7 51 µA µA IVOSNSn+ VOSNSn+ Leakage Current VVOSNSn+ = 28V 290 μA tONn(MIN) Minimum On-Time (Note 4) 60 ns VRUNn RUN n Turn-On/-Off Thresholds RUN n Input Turn-On Threshold, RUNn Rising RUN n Hysteresis l 1.08 1.2 130 1.32 V mV IRUNn RUN n Leakage Current RUN n = 3.3V l 0.1 50 nA Oscillator and Phase-Locked Loop (PLL) fOSCn Oscillator Frequency Accuracy VINn = 12V, ISETna = 5V, and: fSETn Open-Circuit RfSETn = 57.6kΩ (See fSN Specification) l 360 400 1.95 440 kHz MHz fSYNCn PLL Synchronization Capture Range VINn = 12V, ISETna = 5V, CLKINn Driven with a GND Referred Clock Toggling from 0.4V to 1.2V and Having a Clock Duty Cycle: From 10% to 90%; fSETn Open Circuit From 40% to 60%; RfSETn = 57.6kΩ 250 1.3 550 3 kHz MHz VCLKINn CLKIN n Input Threshold VCLKINn Rising VCLKINn Falling 1.2 0.4 V V ICLKINn CLKIN n Input Current VCLKINn = 5V VCLKINn = 0V –20 230 –5 500 μA μA Power Good Feedback Input and Power Good Output OVPGDFBn Output Overvoltage PG00D n Upper Threshold PGDFB n Rising l 620 645 675 mV UVPGDFBn Output Undervoltage PGOOD n Lower Threshold PGDFB n Falling l 525 555 580 mV ∆VPGDFBn PGOOD n Hysteresis PGDFB n Returning 8 mV RPGDFBn Resistor Between PGDFB1 n and SVOUTn– 4.94 4.99 5.04 kΩ RPGOODn PGOOD n Pull-Down Resistance VPGOODn = 0.1V, VPGDFBn < UVPGDFBn or VPGDFBn > OVPGDFBn 700 1500 Ω IPGOODn(LEAK) PGOOD n Leakage Current VPGOODn = 3.3V, UVPGDFBn < VPGDFBn < OVPGDFBn 0.1 1 μA |
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