LTM4651 datasheet(7/54 Pages) AD

7 / 54 page

LTM4655

Rev. 0

For more information www.analog.com

ELECTRICAL CHARACTERISTICS The

denotes the specifications which apply over the specified internal

operating temperature range (Note 2). Specified as each individual output channel (Note 5). TA = 25°C, Test Circuit 2 (negative-

VOUTn–, inverting buck-boost configuration with VOUTn+ = GND), VINn = 12V and electrically connected to SVINn, RUNn–GND = 3.3V,

ISET

na–SVOUTn– = 24V, EXTVCCn = GND, CLKINn open circuit, RfSETn = 57.6kΩ and RISETn = 480kΩ and voltages referred to GND

unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

Input Specifications

VINn(UVLO)

SVINn Undervoltage Lockout Threshold SVINn Rising

SVINn Falling

Hysteresis

2.1

400

3.2

2.5

700

3.6

2.8

IINRUSH(VINn)

Input Inrush Current at Start-Up

CINHn = 4.7μF, CDn = 4.7μF × 2, COUTHn = 47μF ×

2; IOUTn– = 0A, ISETna Electrically Connected to

ISET

1.1

IQ(SVINn)

Input Supply Bias Current

Shutdown, RUN

n = GND

RUN

n–GND = 3.3V

450

μA

IS(VINn)

Input Supply Current

CLKIN

n Open Circuit, IOUTn– = 1.25A

3.0

IS(VINn, SHUTDOWN)

Input Supply Current in Shutdown

Shutdown, RUN

n = GND

µA

Output Specifications

IOUTn–

VOUTn– Output Continuous Current Range VINn =12V,RegulatingVOUTn– =–24VatfSWn =1MHz

VINn = 12V, Regulating VOUTn– = –5V at fSWn = 550kHz

(See Note 3. Capable of Up to 4A Output Current

for Some Combinations of VINn, VOUTn– and fSWn)

1.25

∆VOUTn(LINE)–/VOUTn– Line Regulation Accuracy

IOUTn– = 0A, 3.6V ≤ VINn ≤ 16V, ISETna–SVOUTn– =

24V, CLKIN

n Driven by 1.8MHz Clock

0.05

0.25

∆VOUTn(LOAD)–/VOUTn– Load Regulation Accuracy

VINn = 12V, 0A ≤ IOUTn– ≤ 1.25A, CLKINn Driven by

1.5MHz Clock, RfSETn = 57.6kΩ, and RISETn = 480kΩ

0.05

0.75

VOUTn(AC)–

Output Voltage Ripple, VOUTn–

VINn = 12V, ISETna–SVOUTn– = 5V

mVP-P

fSN

VOUTn– Ripple Frequency

VINn = 12V, ISETna–SVOUTn– = 5V

1.7

1.95

2.2

MHz

∆VOUTn(START)–

Turn-On Overshoot

tSTARTn

Turn-On Start-Up Time

Delay Measured from VINn Toggling from 0V

to 12V to PGOOD

n Exceeding 3V Above GND;

PGOOD

n Having a 100kΩ Pull-Up to 3.3V with

Respect to GND, VPGFBn Resistor Divider Network

as Shown in Test Circuit 2, RISETna = 480kΩ,

ISET

na Electrically Connected to ISETnb, and

CLKIN

n Driven with 1.2MHz Clock

∆VOUTn(LS)–

Peak Output Voltage Deviation for

Dynamic Load Step

IOUTn–: 0A to 1A and 1A to 0A Load Steps in 1μs,

COUTHn = 47µF × 2

400

tSETTLEn

Settling Time for Dynamic Load Step

IOUTn–: 0A to 1A and 1A to 0A Load Steps in 1μs,

COUTH2 = 47µF × 2 X5R

µs

IOUTn(OCL)–

IOUTn– Output Current Limit

1.7

Control Section

IISETna

Reference Current of ISET

na Pin

VISETna–SVOUTn– = 0.5V, 3.6V ≤ VINn ≤ 28V

0V ≤ VISETna–SVOUTn– ≤ VINn–SVOUT– ≤ 40V

49.3

50.7

µA

IVOSNSn+

VOSNSn+ Leakage Current

VOSNSn+ – SVOUTn– = 28V

290

μA

tONn(MIN)

Minimum On-Time

(Note 4 )

VRUNn

RUN

n Turn-On/-Off Thresholds

RUN

n Input Turn-On Threshold, RUNn Rising

RUN

n Hysteresis

(RUN

n Thresholds Measured with Respect to GND)

1.08

1.2

130

1.32

IRUNn

RUN

n Leakage Current

VINn = 12V, RUNn–GND = 3.3V

0.1

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