NB6L16DR2 datasheet(1/12 Pages) ONSEMI

부품명	NB6L16DR2

상세설명	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer

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September, 2004 − Rev. 4

1

Publication Order Number:

NB6L16/D

NB6L16

2.5V / 3.3V Multilevel Input to

Differential LVPECL/LVNECL

Clock or Data

Receiver/Driver/Translator

Buffer

The NB6L16 is a high precision, low power ECL differential clock

or data receiver/driver/translator buffer. The device is functionally

equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With

output transition times of 70 ps, it is ideally suited for high frequency,

low power systems. The device is targeted for Backplane buffering,

GbE clock/data distribution, Fibre Channel distribution and SONET

clock/data distribution applications.

Input accept LVNECL (Negative ECL), LVPECL (Positive ECL),

LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV

ECL signals.

The VBB pin, an internally generated voltage supply, is available to

this device only. For single−ended input conditions, the unused

differential input is connected to VBB as a switching reference voltage.

VBB may also rebias AC coupled inputs. When used, decouple VBB

and VCC via a 0.01 mF capacitor and limit current sourcing or sinking

to 0.5 mA. When not used, VBB should be left open.

• Maximum Input Clock Frequency w 6 GHz Typical

• Maximum Input Data Rate Frequency w 6 Gb/s Typical

• Low 12 mA Typical Power Supply Current

• 70 ps Typical Rise/Fall Times

• 130 ps Input Propagation Delay

• On−Chip Reference for ECL Single−Ended Input − V

BB Output

• PECL Mode Operating Range:

VCC = 2.375 V to 3.465 V with VEE = 0 V

• NECL Mode Operating Range:

VCC = 0 V with VEE = −2.375 V to −3.465 V

• Open Input Default State

• LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input

Compatible

• Pb−Free Packages are Available

A

= Assembly Location

L

= Wafer Lot

Y

= Year

W

= Work Week

MARKING

DIAGRAMS*

ALYW

6L16

SOIC−8

D SUFFIX

CASE 751

1

8

TSSOP−8

DT SUFFIX

CASE 948R

1

8

1

8

*For additional marking information, refer to

Application Note AND8002/D.

6L16

ALYW

1

8

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

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유사한 부품 번호 - NB6L16DR2

제조업체	부품명	데이터시트	상세설명
ON Semiconductor	NB6L16DR2	188Kb / 12P	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer March, 2007 ??Rev. 6
	NB6L16DR2G	188Kb / 12P	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer March, 2007 ??Rev. 6
	NB6L16DR2G	266Kb / 12P	Multilevel Input to Differential Buffer August, 2016 ??Rev. 9

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유사한 설명 - NB6L16DR2

제조업체	부품명	데이터시트	상세설명
ON Semiconductor	NBSG16M	81Kb / 12P	2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2004 ??Rev. 3
	NB6L11	114Kb / 12P	2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR April, 2004 ??Rev. 2
	NB6L611	146Kb / 9P	2.5V / 3.3V 1:2 Differential LVPECL Clock / Data Fanout Buffer December, 2006 ??Rev. 0
	NB6L11	212Kb / 12P	2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator November, 2006 ??Rev. 6
	NB6L16	188Kb / 12P	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer March, 2007 ??Rev. 6
	NB7L572	161Kb / 9P	2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator December, 2008 ??Rev. 1
	NB7L585	159Kb / 9P	2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer / Translator December, 2009 ??Rev. 1
	NB7L572	140Kb / 11P	2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator June, 2012 ??Rev. 2
	NB7L585	94Kb / 9P	2.5V / 3.3V Differential 2:1 Mux Input to 1:6 LVPECL Clock/Data Fanout Buffer Translator July, 2014 ??Rev. 2
	NBSG16M	143Kb / 12P	Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer June, 2014 ??Rev. 9

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