NB6L16

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2

1

2

3

45

6

7

8

Q

D

NC

Figure 1. Pinout (Top View) and Logic Diagram

R2

R2

R1

R1

Q

D

Table 1. PIN DESCRIPTION

Pin

Name

I/O

Default State

Description

1

NC

−

−

No Connect. The NC pin is electrically connected to the die and MUST

be left open.

2

D

LVDS, CML, LVPECL,

LVNECL, LVTTL, LVCMOS

Input

LOW

Non−inverted differential clock/data input. Internal 75 k

37.5 k

3

D

LVDS, CML, LVPECL,

LVNECL, LVTTL, LVCMOS

Input

HIGH

Inverted differential clock/data input. Internal 37.5 k

4

−

−

Internally generated ECL reference voltage supply.

5

−

−

Negative power supply voltage.

6

Q

ECL Output

Inverted differential ECL output. Typically terminated with 50

W resistor

7

Q

ECL Output

Non−inverted differential ECL output. Typically terminated with 50

W

8

−

−

Positive power supply voltage.

Table 2. ATTRIBUTES

Characteristics

Value

Internal Input Default State Resistor

(R1)

37.5 k

W

Internal Input Default State Resistor

(R2)

75 k

W

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 100 V

> 1 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 1.125 in

Transistor Count

167

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.