VT8601 Apollo ProMedia
Revision 1.3 September 8, 1999
-42-
Device 0 Bus 0 Host Bridge Registers
7HFKQRORJLHV ,QF
:H&
:H&RRQQHFW
QQHFW
Device 0 Offset 69 – DRAM Clock Select (00h) ..............RW
7-6
DRAM Operating Frequency Select ................. RW
Rx68[1-0]
Rx69[7-6]
CPU/DRAM
00
00
66/66
(default)
00
01
66/100
01
00
100/100
01
10
100/66
01
01
100/133
10
00
133/133
10
10
133/100
5
256M bit DRAM Support
0
Disable ...................................................default
1
Enable (DCLKRD becomes output)
4
DRAM Controller Command Register Output
0
Disable ...................................................default
1Enable
3
Fast DRAM Precharge for Different Bank
0
Disable ...................................................default
1Enable
2
DRAM 4K Pages (for 64Mbit DRAM)
0
Disable ...................................................default
1Enable
1
Registered DIMM Support
0
Disable ...................................................default
1Enable
0
Reserved
........................................ always reads 0
Device 0 Offset 6A - Refresh Counter............................. RW
7-0
Refresh Counter (in units of 16 CPUCLKs)
00 DRAM Refresh Disabled....................... default
01 32 CPUCLKs
02 48 CPUCLKs
03 64 CPUCLKs
04 80 CPUCLKs
05 96 CPUCLKs
……
The programmed value is the desired number of 16-
CPUCLK units minus one.
Device 0 Offset 6B - DRAM Arbitration Control (01h) RW
7-6
Arbitration Parking Policy
00 Park at last bus owner ............................ default
01 Park at CPU side
10 Park at AGP side
11 Reserved
5
Fast Read to Write Turnaround
0
Disable................................................... default
1Enable
4
Memory Module Configuration ..........................RO
0
Normal Operation .................................. default
1
Unused Outputs Tristated (RASB#, CASB#,
CKE, MAB, DCLKO)
This bit is latched from MAB7# at the rising edge of
RESET#.
3
MD Bus Second Level Strength Control
0
Normal slew rate control........................ default
1
More slew rate control
2
CAS Second Level Strength Control
0
Normal slew rate control........................ default
1
More slew rate control
1
Virtual Channel-SDRAM
0
Disable................................................... default
1Enable
0
Multi-Page Open
0
Disable (page registers marked invalid and no
page register update which causes non page-
mode operation)
1
Enable .................................................... default
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