LTC2430IGN datasheet(10/40 Pages) LINER

10 / 40 page

LTC2430/LTC2431

24301f

Figure 1

FU CTIO AL BLOCK DIAGRA

AUTOCALIBRATION

AND CONTROL

DAC

DECIMATING FIR

INTERNAL

OSCILLATOR

SERIAL

INTERFACE

ADC

∑

∫

GND

VCC

IN+

IN–

SDO

SCK

REF+

REF –

(INT/EXT)

2431 FD

–

TEST CIRCUITS

1.69k

SDO

2431 TA03

Hi-Z TO VOH

VOL TO VOH

VOH TO Hi-Z

CLOAD = 20pF

1.69k

SDO

2431 TA04

Hi-Z TO VOL

VOH TO VOL

VOL TO Hi-Z

CLOAD = 20pF

VCC

SDO (Pin 8): Three-State Digital Output. During the Data

Output period, this pin is used as the serial data output.

When the chip select CS is HIGH (CS = VCC), the SDO pin

is in a high impedance state. During the Conversion and

Sleep periods, this pin is used as the conversion status

output. The conversion status can be observed by pulling

CS LOW.

SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal

Serial Clock Operation mode, SCK is used as the digital

output for the internal serial interface clock during the Data

Output period. In External Serial Clock Operation mode,

SCK is used as the digital input for the external serial

interface clock during the Data Output period. A weak

internal pull-up is automatically activated in Internal Serial

Clock Operation mode. The Serial Clock Operation mode is

determined by the logic level applied to the SCK pin at

power up or during the most recent falling edge of CS.

FO (Pin 10): Frequency Control Pin. Digital input that

controls the ADC’s notch frequencies and conversion

time. When the FO pin is connected to VCC (FO = VCC), the

converter uses its internal oscillator and the digital filter

first null is located at 50Hz. When the FO pin is connected

to GND (FO = OV), the converter uses its internal oscillator

and the digital filter first null is located at 60Hz. When FO

is driven by an external clock signal with a frequency fEOSC,

the converter uses this signal as its system clock and the

digital filter first null is located at a frequency fEOSC/2560.

PI FU CTIO S (LTC2431)

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