LTC2430IGN datasheet(13/40 Pages) LINER

13 / 40 page

LTC2430/LTC2431

24301f

above +FS. If both Bit 21 and Bit 20 are LOW, the

differential input voltage is below –FS.

The function of these bits is summarized in Table 1.

Table 1. LTC2430/LTC2431 Status Bits

Bit 23

Bit 22 Bit 21 Bit 20

Input Range

EOC

DMY

SIG

MSB

VIN ≥ 0.5 • VREF

≤ VIN < 0.5 • VREF

–0.5 • VREF ≤ VIN < 0V

VIN < – 0.5 • VREF

Bits 20-0 are the 21-bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

SCK clock pulses are ignored by the internal data out shift

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 23 (EOC) can be captured on the first rising

edge of SCK. Bit 22 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 23rd SCK and may be latched on

the rising edge of the 24th SCK pulse. On the falling edge

of the 24th SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 22) for the next conversion cycle. Table 2 summarizes

the output data format.

As long as the voltage on the IN+ and IN– pins is maintained

within the – 0.3V to (VCC + 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage VIN from –FS = – 0.5 • VREF to

+FS = 0.5 • VREF. For differential input voltages greater than

Table 2. LTC2430/LTC2431 Output Data Format

Differential Input Voltage

Bit 23

Bit 22

Bit 21

Bit 20

Bit 19

Bit 18

Bit 17

…

Bit 0

VIN*

EOC

DMY

SIG

MSB

LSB

VIN* ≥ 0.5 • VREF**

0110

…

0.5 • VREF** – 1LSB

0101

…

0.25 • VREF**

0101

…

0.25 • VREF** – 1LSB

0100

…

0100

…

–1LSB

0011

…

– 0.25 • VREF**

0011

…

– 0.25 • VREF** – 1LSB

0010

…

– 0.5 • VREF**

0010

…

VIN* < –0.5 • VREF**

0001

…

*The differential input voltage VIN = IN+ – IN–.

**The differential reference voltage VREF = REF+ – REF–.

Figure 3. Output Data Timing

MSB

SIG

“0”

BIT 0

LSB

BIT 19

BIT 20

BIT 21

BIT 22

SDO

SCK

EOC

BIT 23

SLEEP

DATA OUTPUT

CONVERSION

2431 F03

Hi-Z

APPLICATIO S I FOR ATIO

LTC2430IGN 데이터시트(PDF) 13 Page - Linear Technology

LTC2430IGN 데이터시트(HTML) 13 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

데이터시트 다운로드

링크 URL