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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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A6986ITR 데이터시트(PDF) 35 Page - STMicroelectronics |
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A6986ITR 데이터시트(HTML) 35 Page - STMicroelectronics |
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35 / 62 page  Figure 40. Slave-to-master mode transition The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the soft-start begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is triggered regardless of FSW resistor value, that otherwise counts to design the slope compensation. The same considerations above are also valid. The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see Section 3 ): • Low level < VSYN THL = 0.7 V sinking 5 mA • High level > VSYN THH = 1.2 V sourcing 0.7 mA Figure 41. Master driving capability to synchronize the A6986I A6986I Synchronization DS13481 - Rev 2 page 35/62 |
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