ADRV9002BBCZ datasheet(21/92 Pages) AD

21 / 92 page

Data Sheet

ADRV9002

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 21 of 92

Figure 3. Pin Configuration

Table 17. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

A1, A2, A13, A14, B2 to B5,

B10 to B13, C2, C5, C10, C13,

D1 to D6, D9 to D14, E6, E9,

F1 to F3, F6 to F9, F12 to F14,

G2, G13, J1 to J14

Input

VSSA

Analog Ground (VSSA).

A3, A4

Input

EXT_LO2+, EXT_LO2−

Differential External LO Input 1 (LO1). If EXT_LO2+ and EXT_LO2− are used for the external LO1, the

input frequency must be 2× or higher than the desired carrier frequency. For an LO range from 500 MHz

to 1 GHz, a 1× multiplier is available. If unused, connect EXT_LO2+ and EXT_LO2− to VSSA.

Input

VRFVCO2_1P3

1.3 V Internal LDO Regulator Input Supply for RF External LO Input 2 (LO2) VCO and LO Generation

Circuitry. VRFVCO2_1P3 is sensitive to supply noise.

Input and

Output

VRFLO2_1P0

1.0 V Internal Supply Node for RF LO2 LO Generation Circuitry. Connect VRFLO2_1P0 together with

VRFVCO2_1P0 and bypass with a 4.7 µF capacitor when the internal LDO regulator operated from the

VRFVCO2_1P3 input is in use. Provide a 1.0 V supply to VRFLO2_1P0 when the internal LDO regulator

that is operated from VRFVCO2_1P3 is not in use.

Input

MODEA

Use MODEA to configure the boot up option for the DEV_CLK_IN± inputs and the DEV_CLK_OUT

output. Connect MODEA to VSSA to enable the differential clock receiver at the DEV_CLK_IN± pins.

Connect MODEA to a voltage level higher than any VSSA to enable either the single-ended clock at

DEV_CLK_IN+ or the crystal oscillator resonator at both of the DEV_CLK_IN± pins.

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