5.1.2

PCB layout considerations

For correct operation, it is advised to add 10 nF decoupling capacitors as close as possible to the power supply

pins.

Minimizing the leakage from sensitive high impedance nodes on the inputs of the TSU112IY can be performed

with a guarding technique. The technique consists of surrounding high impedance tracks by a low impedance

track (the ring). The ring is at the same electrical potential as the high impedance node.

Therefore, even if some parasitic impedance exists between the tracks, no leakage current can flow through them

as they are at the same potential (see Figure 1).

5.2

Rail-to-rail input

The TSU112IY is built with two complementary PMOS and NMOS input differential pairs. Thus, the device has a

The TSU112IY has been designed to prevent phase reversal behavior.

5.3

Input offset voltage drift overtemperature

The maximum input voltage drift variation overtemperature is defined as the offset variation related to the offset

value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and

the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be

compensated during production at application level. The maximum input voltage drift over temperature enables

the system designer to anticipate the effect of temperature variations.

The maximum input voltage drift over temperature is computed using Equation 1.

Equation 1

∆T

max

( ) V

(

)

–

T 25 °C

–

=

°C

Where T = -40 °C and 125 °C.

The TSU112IY datasheet maximum values are guaranteed by measurements on a representative sample size

TSU112IY

Rail-to-rail input

DS13616 - Rev 1

page 19/32