EM78P152S datasheet(11/52 Pages) ETC1

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EM78P152/3S

8-Bit Microcontroller with OTP ROM

Product Specification (V1.8) 09.08.2009

• 7

(This specification is subject to change without further notice)

The Data Memory Configuration is as follows:

Address

R PAGE Registers

IOC PAGE Registers

(IAR)

Reserve

(TCC)

CONT

(Control Register)

(PC)

Reserve

(Status)

Reserve

(RSR)

Reserve

(Port 5)

IOC5

(I/O Port Control Register)

(Port 6)

IOC6

(I/O Port Control Register)

Reserve

IOCB

(Pull-down Register)

Reserve

IOCC

(Open-drain Control)

Reserve

IOCD

(Pull-high Control Register)

Reserve

IOCE

(WDT Control Register)

(Interrupt Status)

IOCF

(Interrupt Mask Register)

General Registers

Figure 5-3 Data Memory Configuration

5.1.4 R3 (Status Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

GP1

GP0

Bit 7 (RST): Bit for reset type

0 : Set to 0 if the device wakes up from other reset type

1 : Set to 1 if the device wakes up from sleep mode on a pin change

Bits 6 ~5 (GP1 ~ GP0): General-purpose read/write bits

Bit 4 (T):

Time-out bit

Set to “1” with the "SLEP" and "WDTC" commands, or during power up;

and reset to “0” by WDT time-out.

Bit 3 (P):

Power down bit

Set to “1” during power on or by a "WDTC" command; and reset to “0” by

a "SLEP" command.

Bit 2 (Z):

Zero flag

Set to "1" if the result of an arithmetic or logic operation is zero.

Bit 1 (DC): Auxiliary carry flag

Bit 0 (C):

Carry flag

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