MCP37D11-80ESLASHTE datasheet(45/136 Pages) MICROCHIP

45 / 136 page

 2020 Microchip Technology Inc.

DS20006381A-page 45

MCP37D11-80: 80 MSPS 12-BIT PIPELINED ADC

TABLE 4-7:

RECOMMENDED PLL CHARGE PUMP AND LOOP FILTER BIT SETTINGS

PLL Charge Pump and Loop Filter

Parameter

fQ =fREF/PLL_REFDIV

fQ<5 MHz

5 MHz ≤ fQ <25 MHz

fQ ≥ 25 MHz

PLL_CHAGPUMP<3:0>

0x04

PLL_RES<4:0>

0x1F

0x07

PLL_CAP3<4:0>

0x07

0x02

0x07

PLL_CAP2<4:0>

0x07

0x01

0x08

PLL_CAP1<4:0>

0x07

0x01

0x08

TABLE 4-8:

EXAMPLE OF PLL CONTROL BIT SETTINGS FOR fS = 80 MHz WITH fREF = 40 MHz

PLL Control Parameter

Value

Descriptions

fREF

40 MHZ

fREF is coming from the external clock input

Target fS(1)

80 MHZ

ADC sampling frequency

Target fVCO(2)

1.2 GHZ

Range of fVCO = 1.0375 GHz – 1.325 GHz

Target fQ(3)

10 MHZ

fQ = fREF/PLL_REFDIV (See Table 4-7)

PLL Reference Divider (R)

PLL_REFDIV<9:0> = 0x004

PLL Prescaler (N)

120

PLL_PRE<11:0> = 0x078

PLL Output Divider

PLL_OUTDIV<3:0> = 0xF

Note 1:

fS =fVCO/PLL_OUTDIV = 1.2 GHz/15 = 80 MHz

fVCO = (N/R) x fREF = (30) x 40 MHz = 1.2 GHz

fQ should be maximized for the best noise performance.

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