L6911E

14/20

Figure 9. Voltage regulation with droop function block scheme

It results:

Because in the interested range |Gloop|>>1.

To obtain a flat shape, the relationship considered will naturally follow.

VRM Demo Board Description

Figure 10 shows the schematic circuit of the VRM evaluation board. The design has been developed for a VRM

8.5 Flexible Motherboard applicaton delivering up to 28.5A.

An additional circuit sense a Vtt bus (1.2V typ.) and generate a 2.5mS (typ.) delayed Vtt_PWRGD signal when

this rail is over 1.1V. The assertion of the Vtt_PWRGD signal enables the device together with the ENOUT input.

Figure 10. Schematic Circuit

Av (s)

R(s )

V out

Vc om p

Io ut

d

s

L

s

OUT

R

τ

τ

⋅

+

⋅

+

⋅

1

1

Z

OU T

V

o

I

LOA D

----------------

R

d

1s

τ

L

+

1s

τ

d

+

------------------

G

LOOP

1G

L OOP

+

-----------------------------

⋅⋅

R

OUT

1s

τ

L

+

1s

τ

d

+

------------------

⋅

==

=

L6911E CONNECTOR EVALUATION KIT REV. 1 .1

L2

L1

R7

R8

R9

C1-3

C10

C4-9

C17

Q3,Q4 ,Q5

Q1,Q2

D2

C12

F1

16

17

13

14

2

4

5

6

7

8

U1

L6911E

+5 VIN

+12Vcc

VOUTCORE

Vss

10

15

9

3

20

18

11

19

12

1

VCC

GND

VID0

VID1

VID2

VID3

VID4

SS

OSC

OCSET

UGATE

PHASE

LGATE

PGND

PGOOD

VSEN

R3

R4

R5

R2

C18

C19

C20

VID0

VID1

VID2

VID3

VID25mV

C11

D1

R6

R1

Vtt_PGOOD

UZ

TLC7701

8

2

4

7

3

5

6

1

OUTEN

Vtt_sense

Vdd

NOT RESIN

GND

SENSE

CT

NOT RESET

CONTRO L

RESET

R14

C15

R12

Q6

R10

R11

C16

C14

Q7

C13

R13

D3

PWRGD

R15