PIMXRT516SCVL2A datasheet(64/124 Pages) NXP

64 / 124 page

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

Figure 25. FlexSPI output timing in SDR mode

4.5.2.2.2

DDR mode

NOTE

TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1 register, the

default values are shown above. Please refer to the i.MXRT1160 Reference

Manual (IMXRT1160RM) for more details.

Figure 26. FlexSPI output timing in DDR mode

4.6

Display and graphics

The following sections provide information about display and graphic interfaces.

Table 59. FlexSPI output timing in DDR mode

Symbol

Parameter

Min

Max

Unit

Frequency of operation1

1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing

specifications.

—

166

MHz

Tck

SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)

6.0

—

TDVO

Output data valid time

—

2.2

TDHO

Output data hold time

0.8

—

TCSS

Chip select output setup time

3 x TCK / 2 - 0.7 —

TCSH

Chip select output hold time

3 x TCK / 2 + 0.8 —

T CSS

T CK

TCSH

TDVO

TDHO

TDVO

TDHO

SCK

SIO[0:7]

T CSS

T CK

TDVO

TDHO

TDVO

TDHO

TCSH

SCK

SIO[0:7]

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