MCP3464 datasheet(74/108 Pages) MICROCHIP

74 / 108 page

MCP3461/2/4

DS20006180D-page 74

 2019-2021 Microchip Technology Inc.

6.8.2

CONVERSION CYCLE START

INTERRUPT

This interrupt is the only one that is selectable and the

only one not present in the STATUS byte on SDO and

the IRQ register. It is only available on the IRQ pin. The

user can enable or disable this output using:

•[EN_STP] = 1: Conversion start interrupt output is

enabled (default).

•[EN_STP] = 0: Conversion start interrupt output is

disabled.

This interrupt marks the beginning of a conversion

cycle. In case of a One-Shot mode or Continuous mode

conversion in MUX mode, it marks the start of the

sampling in the first conversion (happening after the

ADC start-up delay of 256 DMCLK periods). In case of

a SCAN mode, it marks the start of the sampling in the

first conversion of the first SCAN mode cycle. The host

MCU can utilize this interrupt to synchronize the start of

the ADC conversion and manage synchronous events

together with the conversion process. See Figure 6-15

for more details.

This interrupt output generates a falling edge on the IRQ

pin and is cleared automatically after a short time, TSTP.

FIGURE 6-15:

Conversion Start IRQ Timing Diagram.

6.8.3

POR INTERRUPT

The POR interrupt provides information to the user that

either a POR event has happened previously or if the

part is in a POR state when the IRQ pin is used.

This interrupt is implemented with three different and

independent mechanisms: STATUS byte on SDO, IRQ

6.8.3.1

STATUS Byte on SDO

When the device powers up, on the first STATUS byte

transmitted on SDO (first communication), the

POR_STATUS is logic low. Once the STATUS byte has

been transmitted, the POR_STATUS bit appears as ‘1’

until the part is powered down. If between two STATUS

byte transmissions, a POR event happens once again,

and if the part is properly repowered up, the POR_STA-

TUS bit on SDO will appear as equal to ‘0’ on the latter

reading. This mechanism can only work when the power

supplies are back above the POR thresholds, on the

analog and digital cores, as retrieving data from the SPI

port is not possible when the device is in a POR state.

6.8.3.2

IRQ Register Status Bit

When the device is powered up, the POR_STATUS bit

in the IRQ register will be reset to ‘0’. Once the IRQ

reset again to ‘1’.

If, between two readings of the IRQ register, a POR

event happens once again, the IRQ register Status bit

will appear as equal to ‘0’ on the second reading. This

mechanism can only work when the power supplies are

back above the POR thresholds on the analog and

digital cores.

ADC_MODE

IRQ

TADC_SETU P

TCON V

TSTP

Conversion

Start IRQ

(EN_STP =

Data Ready

IRQ

ADC Shutdown

ADC STATUS

1st Conversi on in

either MU X or SC AN mo de

Sta rt-u p

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