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MCP3464T-E/ST 데이터시트(PDF) 60 Page - Microchip Technology

부품명 MCP3464T-E/ST
상세설명  Two/Four/Eight-Channel, 153.6 ksps, Low Noise, 16-Bit Delta-Sigma ADC
PDF  108 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3464T-E/ST 데이터시트(HTML) 60 Page - Microchip Technology

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MCP3461/2/4
DS20006180D-page 60
 2019-2021 Microchip Technology Inc.
6.2.2
DEVICE ADDRESS BITS (CMD[7:6])
The SPI interface of the MCP3461/2/4 devices is
addressable, which means that multiple devices can
communicate on the same SPI bus with only one chip
select line for all devices. Each device communication
starts by a CS falling edge, followed by the clocking of
the device address (CMD[7:6]). Each device contains
an internal device address which the device can
respond to.
This device address is coded on two bits, so four possible
addresses are available. The address is hard-coded
within the device and should be determined at the order-
ing of the device. The device address is part of the device
markings to avoid potential confusion (see Section 9.1
“Package Marking Information(2)”). When the
CMD[7:6] bits match the device address, the communi-
cation proceeds and the part will execute the commands
defined in the control byte and its subsequent data bytes.
When the CMD[7:6] bits do not correspond to the
device address hard-coded in the device, the com-
mand is ignored. In this case, the SDO output will
become high-impedance, which prevents bus conten-
tion errors when multiple devices are connected on the
same SPI bus (see Figure 6-3). The user has to exit
from this communication through a CS rising edge to
be able to launch another command.
6.2.3
COMMAND ADDRESS BITS
(CMD[5:2])
The COMMAND byte contains four address bits
(CMD[5:2]) that can serve two purposes. In case of a
register write or read access, they define at which
register address the first read/write is performed. In
case of a Fast command, they determine which Fast
command is executed by the device. In case of a Write
command on a read-only register, the command is not
executed and the communication should be aborted
(CS rising edge) to place another command. All
registers can be read; there is no undefined address in
the register map.
6.2.4
COMMAND-TYPE BITS (CMD[1:0])
The last two bits of the COMMAND byte define the
command type. These bits are an extension of the typical
read/write bits present in most SPI communication proto-
cols. The two bits define four possible command types:
Incremental Write, Incremental Read, Static Read and
Fast command. Changing command type within the
same communication (while CS is logic low) is not
possible. The communication has to be stopped (CS
rising edge) and restarted (CS falling edge) to change its
command type. The list of possible commands, their type
and their possible command addresses are described in
Table 6-1.
TABLE 6-1:
COMMAND TYPES DESCRIPTION TABLE
CMD[5:2]
CMD[1:0]
Command Description
0xxx
00
Don’t Care
100x
00
Don’t Care
1010
00
ADC Conversion Start/Restart Fast Command (Overwrites ADC_MODE[1:0] = 11)
1011
00
ADC Standby Mode Fast Command (Overwrites ADC_MODE[1:0] = 10)
1100
00
ADC Shutdown Mode Fast Command (Overwrites ADC_MODE[1:0] = 00)
1101
00
Full Shutdown Mode Fast Command (Overwrites CONFIG0[7:0] = 0x00)
1110
00
Device Full Reset Fast Command (Resets Whole Register Map to Default Value)
1111
00
Don’t Care
ADDR
01
Static Read of Register Address, ADDR
ADDR
10
Incremental Write Starting at Register Address, ADDR
ADDR
11
Incremental Read Starting at Register Address, ADDR



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