ACE25QC200GL datasheet(21/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Active Status Interrupt (25h)

To simplify the readout of the WIP bit, the Active Status Interrupt Instruction (25h) may be used. It is then

not necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If

the SO line is connected to an interrupt line on the host controller, the host controller may be in sleep mode

until the SO line indicates that the device is ready for the next Instruction

The WIP bit can be read at any time, including during an internally self-timed program or erase operation.

To enable the Active Status Interrupt instruction, the /CS pin must first be asserted and the instruction code

of 25h must be clocked into the device. The value of the SI line after the instruction code being clocked in is

of no significance to the operation.

The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the

/CS pin remains asserted. Additional clocks on the SCK pin are not required. That is, whether the additional

clock on the SCK pin exists is independent of the correct output of the value of WIP. (Figure 6. shows a

case where additional clocks exist). If the WIP bit changes from 1 to 0 while the /CS pin is asserted, the SO

line will change from 1 to 0. (The WIP bit cannot change from 0 to 1 during an operation, so if the SO line

already is 0, it will not change.)

De-asserting the /CS pin will terminate the Active Status Interrupt operation and put the SO pin into a

high-impedance state.

The sequence of issuing ASI instruction is: /CS goes low→ sending ASI instruction code→ WIP data out on

Figure 6. Active Status Interrupt Instruction

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