ACE25QC200GL datasheet(22/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

Write Status Register (01h)

The Write Status Register instruction allows the Status Registers to be written. The writable Status Register

bits include: SRP0, BP[4:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status Register- 2. All other

Status Register bit locations are read-only and will not be affected by the Write Status Register instruction.

LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0.

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register.

Before it can be accepted, a Write Enable (WREN) or Write Enable For Volatile SR instruction must

previously have been executed After the Write Enable (WREN) instruction has been decoded and executed,

the device sets the Write Enable Latch (WEL).

The Write Status Register instruction has no effect on S15(SUS1), S10(SUS2), S1(WEL) and S0(WIP) of

the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched

in. If not, the Write Status Register (WRSR) command is not executed. If

/CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As

soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.

While the Write Status Register cycle is in progress, the Status Register may still be read to check the value

of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status

is reset.

The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3,

BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in

Table5 and Table6.The Write Status Register (WRSR) instruction also allows the user to set or reset the

Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The

Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in

the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware

Protected Mode is entered.

The sequence of issuing WRSR instruction is: /CS goes low→ sending WRSR instruction code→ Status

data on SI→/CS goes high.

The /CS must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be

rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip

Select (/CS) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status

Cycle is completed, and the Write Enable Latch (WEL) bit is reset.

Figure 7. Write Status Register Instruction

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