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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ACE25QC200GLFMLTH 데이터시트(PDF) 25 Page - ACE Technology Co., LTD. |
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ACE25QC200GLFMLTH 데이터시트(HTML) 25 Page - ACE Technology Co., LTD. |
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25 / 64 page  ACE25QC200GL 2M BIT SPI NOR FLASH VER 1.1 25 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on two pins, SI, SO, /WP, and /HOLD. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 11. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. Figure11. Fast Read Quad Output Instruction |
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