ACE25QC200GLFMLTH datasheet(9/64 Pages) ACE

9 / 64 page

ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge

sensitive as well as level sensitive: after power-up, the device does not become selected until a falling

edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have

been High, prior to going Low to start the first operation.

(C)

Device Reset

In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on

reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC

has reached the power on reset threshold voltage.

When VCC has passed the POR threshold, the device is reset.

(D)

Power-down

At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating

voltage to below the power on reset threshold voltage, the device stops responding to any instruction

sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to

follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal

Write cycle in progress).

Active Power and Standby Power Modes

When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device

consumes ICC.

When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the

device then goes in to the Standby Power mode, and the device consumption drops to ICC1.

Hold Condition

The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the

operation of write status register, programming, or erasing in progress.

The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK

signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD

condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD

operation will not end until SCLK being low).

The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if /CS drives high

during HOLD operation, it will reset the internal logic of the device to Standby Mode. To re-start

communication with chip, the /HOLD must be at high and the /CS must be at low.

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