ADA4255ACPZ-R7 datasheet(38/64 Pages) AD

38 / 64 page

Data Sheet

ADA4255

DIGITAL INTERFACE

analog.com

Rev. 0 | 38 of 64

CRC CALCULATION

The checksum, which is 8 bits wide, is generated using the follow-

ing polynomial (with a seed of 0x00):

x8 + x2 + x + 1 (0b100000111)

To generate the checksum, the data is left shifted by 8 bits to create

a number ending in eight Logic 0s. The polynomial is aligned so

that its MSB is adjacent to the leftmost Logic 1 of the data. An

exclusive OR (XOR) function is applied to the data to produce a

new, shorter number. The polynomial is again aligned so that its

MSB is adjacent to the leftmost Logic 1 of the new result, and the

procedure is repeated. This process is repeated until the original

data is reduced to a value less than the polynomial. This is the 8-bit

checksum.

Figure 103. Calculating a CRC Checksum

MEMORY MAP CHECKSUM PROTECTION

For added robustness, a CRC calculation is performed on the

on-chip registers as well. Register 0x03, Register 0x04, and

of these registers change, independent of SPI writes. The CRC is

performed at a rate of 15.26 Hz. Each time the register map is

changed using an SPI write, the CRC is recalculated.

The memory map CRC function is enabled by default. This

function can be disabled via the MM_CRC_ERR_DIS bit

(Register DIGITAL_ERR_DIS). If an error occurs, the

MM_CRC_ERR bit (Register DIGITAL_ERR) trips.

Figure 104. Verifying Data with a CRC Checksum

READ-ONLY MEMORY (ROM) CHECKSUM

PROTECTION

On power-up, all fuse registers are set to the default values.

These default values are held in ROM. For added robustness, a

CRC calculation is performed on the ROM contents as well. This

CRC check is performed on power-up. The ROM CRC function is

enabled by default. This function can be disabled via the ROM_

CRC_ERR_DIS bit (Register DIGITAL_ERR_DIS). If an error oc-

curs, the ROM_CRC_ERR bit (Register DIGITAL_ERR) trips.

SPI READ AND WRITE ERROR DETECTION

The ADA4255 can detect if an invalid register is being addressed.

A read or write to an invalid address trips the SPI_RW_ERR bit

(Register DIGITAL_ERR). The SPI_RW_ERR bit is enabled by

default, and this bit can be disabled via the SPI_RW_ERR_DIS bit

(Register DIGITAL_ERR_DIS).

SPI COMMAND LENGTH ERROR DETECTION

When communicating with the ADA4255, the number of clock

edges on SCLK is monitored to ensure that, when CS returns

high, the total number of clock edges received is divisible by 8.

If the number of SCLK edges is insufficient or in excess, the

SPI_ SCLK_CNT_ERR bit (Register DIGITAL_ERR) trips. The

SPI_SCLK_CNT_ERR is enabled by default, and this bit can be

disabled via the SPI_SCLK_CNT_ERR_DIS bit

(Register DIGITAL_ERR_DIS).

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