CDCDB800 datasheet(9/31 Pages) TI

9 / 31 page

VDD, VDD_R = 3.3 V ± 5 %, −40 °C ≤ TA ≤ 105 °C. Typical values are at VDD = VDD_R = 3.3 V, 25 °C (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CIN

Input capacitance

4.5

COUT

Output capacitance

4.5

IIH

Input leakage current

With internal pull-up/pull-down VIN = VDD

–30

µA

CIN

Input capacitance(1)

4.5

(1)

Voltage swing includes overshoot.

(2)

Not tested in production. Ensured by design and characterization.

(3)

Measured into DC test load.

(4)

VCROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P

is rising.

(5)

Measured from rising edge of CLK_IN to any CKx output.

(6)

Measured from rising edge of any CKx output to any other CKx output.

(7)

Measured into AC test load.

6.6 Timing Requirements

VDD, VDD_R = 3.3 V ± 5 %, −40 °C ≤ TA ≤ 105 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise

noted)

MIN

NOM

MAX

UNIT

SMBUS-COMPATIBLE INTERFACE TIMING

fSMB

SMBus operating frequency

400

kHz

tBUF

Bus free time between STOP and START

4.7

µs

tHD_STA

START condition hold time

SMBCLK low after SMBDAT low

tSU_STA

START condition setup time

SMBCLK high before SMBDAT low

4.7

tSU_STO

STOP condition setup time

tHD_DAT

SMBDAT hold time

300

tSU_DAT

SMBDAT setup time

250

tTIMEOUT Detect SMBCLK low timeout

In terms of device input clock frequency

1e6

cycles

tLOW

SMBCLK low period

4.7

µs

tHIGH

SMBCLK high period

SMBCLK/SMBDAT fall time(1)

300

SMBCLK/SMBDAT rise time(2)

1000

(1)

TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2)

TR = (VILMAX - 0.15) to (VIHMIN + 0.15)

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CDCDB800

SNAS818 – JULY 2021

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