5.4

Setting Pulse-skip Mode Threshold

If an RCLP programming resistor is placed between RCLP pin and IC ground, the clamping voltage level is given by:

output of the current sense amplifier drops to 0.3V.

Note:  The gain with this current amplifier is 5.

Therefore, in terms of the voltage on the sense resistor (input of the current amplifier), 0.3V/5 = 0.06V. As the

converter is usually designed in such a way that its peak is around 0.2V (the peak of Rsense voltage before it starts

to current limit), ratio of 0.06V/0.2V = 0.3 is obtained. In other words, the converter enters pulse-skipping when the

output current is 30% of the maximum designed output current.

5.5

Setting UVLO/Hysteresis Thresholds

Note: A 470k resistor from PG pin to VINS pin is required for guaranteeing proper termination of gate drive pulse

during UVLO.

hysteresis resistor from the output of the UVLO comparator, which provides positive feedback on to the VINS pin, is

also present, as explained in the 3. Pin Configuration section. When the input voltage is rising, in effect, the

UVLO comparator flips and the hysteresis resistor appears connected to 5V (output of the UVLO comparator). The

equivalent configurations are shown in Figure 5-1. After solving the equations, the following example indicates the set

thresholds. The values are as used in Figure 1-2.

Therefore, with the selected resistors, a rising threshold of 39.8V and a falling threshold of 34.8V is achieved.

PD70211

Applications Information

Datasheet

DS00003672A-page 25