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STW4810BHDLF 데이터시트(PDF) 27 Page - STMicroelectronics |
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STW4810BHDLF 데이터시트(HTML) 27 Page - STMicroelectronics |
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27 / 72 page ![]() STw4810 4 Functional description Rev3 27/72 Power control register at address 08h Power control register at address 09h Table 24. Power control register at address 08h Address 1Fh Address 1Eh 15 14 13 12 11 10 98765 43210 Not used 01000 en_clk squarer en_mo nitoring en_ vana not used EN Bits Name Value Settings Default 4 en_clock_squarer 0 1 Disabled Enabled (sine wave signal input) 0 3 en_monitoring 0 1 Disabled / MONITORING = OFF Enabled / VCORE & VIO_VMEM monitoring = ON 1 2 en_vana 0 1 Disabled / VANA = OFF Enabled / VANA = ON 1 Table 25. Power control register at address 09h Address 1Fh Address 1Eh 15 14 13 12 11 10 98765 43210 Not used 01001 vaux_ sleep not used vio_ vmem_ sleep vcore_ sleep EN Bits Name Value Settings Default 4 vaux_sleep 0 1 When PWREN is low: VAUX stays in normal mode VAUX goes in sleep mode (default) 1 2 vio_vmem_sleep 0 1 When PWREN is low: VIO_VMEM stays in normal mode VIO_VMEM goes in sleep mode 1 1 vcore_sleep 0 1 When PWREN is low: VCORE stays in normal mode VCORE goes in sleep mode 1 |
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