STW4810BHDLF datasheet(31/72 Pages) STMICROELECTRONICS

31 / 72 page

STw4810

4 Functional description

Rev3

31/72

Main features:

●

Programmable output voltage, 15 levels from 1.0 V to 1.5 V (VCORE_SEL [3:0] bits of

Power control register -

Table 21)

●

3 power domains:

–

‘Normal mode’ when multimedia processor is in run mode, 600 mA full load

–

‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current

capability.

Fast switching from low current to normal mode.

The regulator is in ‘low current mode’ when multimedia processor is in sleep mode.

PWREN signal indicates that the multimedia processor is about to switch to run

mode. VDDOK signal indicates to the multimedia processor that all supplies are in the

specified range.

Note:

The definition of SLEEP mode is given in section 4.2.3: SLEEP mode.

●

‘Power Down mode’ or ‘Standby Mode’ when regulator is switched off, no consumption

(EN_VCORE bit of Power control register -

Table 27)

●

Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●

Default setting defined by start-up configuration.

4.3.3

VIO_VMEM regulator: DC/DC step- down regulator

VIO_VMEM step-down regulator has the same structure than VCORE.

The VIO_VMEM regulator supplies the IOs of the multimedia processor and its peripherals.

This regulator can be used to supply the memories working with the multimedia processor,

such as DDR-SDRAM. A switched mode power supply - voltage down converter is used to

generate the 1.8 V regulated power supply with very high efficiency.

The master clock (13, 19.2 or 26 MHz) is automatically detected, squared and divided to

generate the SMPS switching clock. When this clock is not available, regulators can run the

internal RC oscillator.

Main features

●

Fixed 1.8 V output voltage

●

Two power domains:

–

‘Normal mode’ when multimedia processor is in run mode - 600 mA full load

–

‘Low current mode’ when multimedia processor is in sleep mode, 5 mA current

capability.

Fast switching from low current to normal mode.

The regulator is in ‘low current mode’ when multimedia processor is in sleep mode.

PWREN signal indicates that the multimedia processor is about to switch to run

mode. VDDOK signal indicates to the multimedia processor that all supplies are in the

specified range.

Note:

The definition of SLEEP mode is given in 4.2.3: SLEEP mode section.

●

Soft start circuitry at start up, from power off to normal mode, when PON ball changes

from “0” to “1”.

●

Default setting defined by start-up configuration.

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