STW8019A datasheet(40/55 Pages) STMICROELECTRONICS

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Control registers

STw8009/STw8019

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5.2.2

Control & power management unit registers

Control and power management unit

standby: In this mode the analog subsystem is supplied by the 1.2 V and the 2.8 /3.3 V, but

the DACs are set in power down mode, via poff[1:2] bits (Reg 130 & 131). Digital to analog

data conversion is disabled.

(*) 0 = disabled (active mode)

1 = standby

Control and power management unit reset

cpmuswrst: Control and power management unit reset

(*) 0 = disabled

1 = control and power management unit software reset

Note:

Bit cpmuswrst is automatically reset to its default value after internal reset generation and

the I2C data transfer is stopped. This reset is kept available for a CLK cycle.

poff1: DAC1 power off, then turn off DAC1 is in a low power consumption mode

0 = disabled (DAC1 active)

(*) 1 = turned off

Note:

As Default value is “1”, Digital processor must write “0” when going from sleep or standby to

active mode.

notzerod1 : null digital data inputed on DAC1

0 = independently of what is coming from the digital part, “0000000000” is forced on

DAC1 input.

(*) 1 = disabled, values issued from DENC are transmitted to DAC1.

pedestalOnd1 : Black level video pedestal active on DAC1

(*) 0 = disabled

1 = video pedestal active

Configuration0

Address:

0x0080

Type: R/W

content

standby

default

0000

Configuration 1

Address:

0x0081

Type: R/W

content

cpmuswrst

default

000

DAC1 control

Address:

0x0082

Type: R/W

content

poff1

notzerod1

pedestal

Ond1

default

000

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