STW8019BS3 datasheet(8/55 Pages) STMICROELECTRONICS

8 / 55 page

Ball/pin information

STw8009/STw8019

8/55

Ball/pin information

Table 1.

Product name ball functions

Ball

Name

Type

Voltage

Description

Vdd

Power

1.2 V

Digital core chip supply

Gndd

GND

0 V

Digital core chip ground

Vdd_IO1

Power

1.8 V

Digital I/O supply

Vss_IO1

GND

0 V

Digital I/O ground

Vdd_IO2

Power

1.8 V

Digital I/O supply

Vss_IO2

GND

0 V

Digital I/O ground

VccA1

Power

2.8 /3.3V

DAC1 matrix analog power supply

VccA2

Power

2.8 /3.3 V

DAC2 matrix analog power supply

VccA3

Power

2.8 /3.3 V

2.8/3.3 V digital feature supply

VccA4

Power

2.8 /3.3 V

2.8 /3.3 V digital feature supply

GNDA1

GND

0 V

DAC1 ground

GNDA2

GND

0 V

DAC2 ground

GNDA3

GND

0 V

2.8 /3.3 V digital feature ground

GNDA4

GND

0 V

Rext ground connection

GNDA5

GND

0 V

Analog ground

Rext

Analog

DAC current reference setting

CLK

Digital Input

1.8 V

27 MHz master pixel clock (pixclk)

G7, G6,

F7, F6,

E7, E6,

D7, D6

YCbCr[0:7]

Digital Input

1.8 V

Time multiplexed 4:2:2 luminance and

chrominance data as defined in CCIR 601

and CCIR 656 (excepted for TTL input

signals)

Hsync

Digital I/O

1.8 V

Horizontal Synchronization signal:

- Input in slave mode, except when sync is

extracted from YcbCr data

- Output in master mode and when sync is

extracted from YcbCr signal.

Vsync

Odd/Even

Digital I/O

1.8 V

Vertical Synchronization – Odd/Even signal:

- Input in slave mode, except when sync is

extracted from YcbCr data

- Output in master mode and when sync is

extracted from YcbCr signal.

SDA

Digital I/O

1.8 V

2 wire serial MPU data line

SCL

Digital Input

1.8 V

2 wire serial MPU clock

Add

Digital input

1.8 V

Device address selection

PORn

Digital input

1.8 V

Power On Reset (Active low)

Suspend

Digital input

1.8 V

Suspend input

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