873033AM

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 19, 2005

10

Integrated

Circuit

Systems, Inc.

ICS873033

V

50

Ω

50

Ω

RTT

Z

Z

FOUT

FIN

RTT =

Z

o

1

((V

3.3V

125

Ω

125

Ω

84

Ω

84

Ω

Z

Z

FOUT

FIN

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

50

Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and mini-

mize signal distortion. Figures 5A and 5B show two different

layouts which are recommended only as guidelines. Other

suitable clock layouts may exist and it would be recommended

that the board designers simulate to guarantee compatibility

across all printed circuit and clock component process varia-

tions.

This section shows examples of 5V LVPECL output termina-

tion. Figure 6A shows standard termination for 5V LVPECL.

The termination requires matched load of 50

Ω resistors pull

down to V

Zo = 50 Ohm

R2

50

Zo = 50 Ohm

5V

3V

PECL

+

-

R1

50

5V

PECL

R4

84

5V

Zo = 50 Ohm

R3

84

R2

125

5V

PECL

PECL

+

-

Zo = 50 Ohm

R1

125

equivalence of Figure 6A. In actual application where the 3V

DC power supply is not available, this approached is nor-

mally used.