PLL620-00DC datasheet(3/7 Pages) PLL

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PLL620-00

Low Phase Noise XO with multipliers (for HF Fund. and 3rd O.T.)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com Rev 09/03/04 Page 3

4. Jitter Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Period jitter RMS

2.5

Period jitter peak-to-peak

At 155.52MHz, with capacitive decoupling

between VDD and GND. Over 10,000 cycles

18.5

Accumulated jitter RMS

2.5

Accumulated jitter peak-to-

peak

At 155.52MHz, with capacitive decoupling

between VDD and GND. Over 1,000,000

cycles.

Random Jitter

“RJ” measured on Wavecrest SIA 3000

2.5

Integrated jitter RMS at

155MHz

Integrated 12 kHz to 20 MHz

0.3

0.4

Period jitter RMS

Period jitter peak-to-peak

At 622.08MHz, with capacitive decoupling

between VDD and GND. Over 10,000 cycles

Accumulated jitter RMS

Accumulated jitter peak-to-

peak

At 622.08MHz, with capacitive decoupling

between VDD and GND. Over 1,000,000

cycles.

Random Jitter

“RJ” measured on Wavecrest SIA 3000

Integrated jitter RMS at

622MHz

Integrated 12 kHz to 20 MHz

1.6

1.8

Note: Higher Q factor of 3rd overtone crystals will result in even better jitter performance.

Measured on Wavecrest SIA 3000

5. Phase Noise Specifications

PARAMETERS

FREQUENCY

@10Hz

@100Hz

@1kHz

@10kHz @100kHz

UNITS

155.52MHz

-75

-95

-125

-140

-145

Phase Noise relative

to carrier

622.08MHz

-75

-95

-110

-125

-120

dBc/Hz

Note: Higher Q factor of 3rd overtone crystals will result in even better phase noise performance.

6. CMOS Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

IOH

VOH= VDD-0.4V, VDD=3.3V

Output drive current

(High Drive)

IOL

VOL = 0.4V, VDD = 3.3V

IOH

VOH= VDD-0.4V, VDD=3.3V

Output drive current

(Standard Drive)

IOL

VOL = 0.4V, VDD = 3.3V

Output Clock Rise/Fall Time

(Standard Drive)

0.3V ~ 3.0V with 15 pF load

2.4

Output Clock Rise/Fall Time

(High Drive)

0.3V ~ 3.0V with 15 pF load

1.2

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