PCIMX6D4AVT08CD datasheet(40/171 Pages) NXP

40 / 171 page

i.MX 6Dual/6Quad Applications Processors for Consumer Products, Rev. 6, 11/2018

NXP Semiconductors

Electrical Characteristics

4.6.3

DDR I/O DC Parameters

The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.

4.6.4

RGMII I/O 2.5V I/O DC Electrical Parameters

The RGMII interface complies with the RGMII standard version 1.3. The parameters in Table 23 are

guaranteed per the operating ranges in Table 6, unless otherwise noted.

Table 22. GPIO I/O DC Parameters

Parameter

Symbol

Test Conditions

Min

Max

Unit

High-level output voltage1

1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be

controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.

Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

Voh

Ioh = -0.1 mA (DSE2 = 001, 010)

Ioh = -1 mA

(DSE = 011, 100, 101, 110, 111)

2 DSE is the Drive Strength Field setting in the associated IOMUX control register.

OVDD – 0.15

—

Low-level output voltage1

Vol

Iol = 0.1 mA (DSE2 = 001, 010)

Iol = 1mA

(DSE = 011, 100, 101, 110, 111)

—0.15

High-Level DC input voltage1, 3

3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

Vih

—

0.7

× OVDD

OVDD

Low-Level DC input voltage1, 3

Vil

—

0.3

× OVDD V

Input Hysteresis

Vhys

OVDD = 1.8 V

OVDD = 3.3 V

0.25

—

Schmitt trigger VT+3, 4

4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

VT+

—

0.5

× OVDD

—

Schmitt trigger VT–3, 4

VT–

—

0.5

× OVDD V

Input current (no pull-up/down)

Iin

Vin = OVDD or 0

-1

μA

Input current (22 k

Ω pull-up)

Iin

Vin = 0 V

Vin = OVDD

—212

μA

Input current (47 k

Ω pull-up)

Iin

Vin = 0 V

Vin = OVDD

—100

μA

Input current (100 k

Ω pull-up)

Iin

Vin = 0 V

Vin= OVDD

—48

μA

Input current (100 k

Ω pull-down)

Iin

Vin = 0 V

Vin = OVDD

—1

μA

Keeper circuit resistance

Rkeep

Vin = 0.3 x OVDD

Vin = 0.7 x OVDD

105

175

PCIMX6D4AVT08CD 데이터시트(PDF) 40 Page - NXP Semiconductors

PCIMX6D4AVT08CD 데이터시트(HTML) 40 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL