AT25SL641 datasheet(32/76 Pages) DIALOG

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AT25SL641

DS-25SL641–113F–12/2018

cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions. When the BUSY

bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 7-21. Page Program Instruction (SPI Mode)

Figure 7-22. Page Program Instruction (QPI Mode)

7.16

Quad Page Program (33h)

The Quad Page Program instruction is use d to program the memory to “0” at previously erased memory areas. The Quad

Page Program uses four pins to transfer address and data: IO0, IO1, IO2 and IO3. This improves performance and data

throughput of lower clock frequencies of less than 5MHz. Systems using faster clock speed will not get more benefit for the

Quad Page Program as the required internal page program time is far more than the time required to clock data in.

To use Quad Page Program, the Quad Enable bit must be set, A Write Enable (06h) instruction must be executed

before the device can accept the Quad Page Program instruction (Status Register-1, WEL = 1). The instruction is

initiated by driving the CS pin low, then sending the instruction code 33h followed by a 24-bit address (A23 - A0) and at

least one data, into the I/O pins. The CS pin must be held low for the entire length of the instruction while data is being

sent to the device. All other functions of Quad Page Program are the same as the standard Page Program. Please

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